Huiming Bu

Title

Vice President: IBM Semiconductors Global R&D and Albany Operations

Bio

Dr. Huiming Bu is responsible for IBM global Semiconductor R&D strategy across world-wide labs. He oversees R&D activities in advanced logic, chiplet and advanced packaging, emerging memory and analog AI hardware at IBM Research. In addition to leading semiconductor technology R&D agenda, Huiming is also responsible for IBM Research Albany Lab site and fab operations.

Huiming has ~20 years of professional experience in semiconductor technology R&D at IBM after he received his Ph.D. in Electrical Engineering from Yale University. Huiming has authored/co-authored 100+ technical publications and holds 100+ patents in semiconductor domain.

Huiming started his technical career at IBM on High-κ/Metal Gate project and then led SOI FinFET research and early development for IBM’s 14nm node technology. After that, Huiming and his team delivered 10nm/7nm technology R&D for IBM and its Joint Development Alliance (JDA) partners. They are now working on 2nm development and 1nm & beyond pathfinding R&D. Recently, as IBM formed Semiconductors division under IBM Research, the footprint has expanded from advanced logic to chiplet & advanced packaging, intelligent fab, cloud based EDA and design.

Publications

Extremely thin SOI (ETSOI) technology: Past, present, and future
- - Kangguo Cheng
  - A. Khakifirooz
  - et al.
- 2010
- IEEE International SOI Conference 2010
Hot-carrier degradation in undoped-body etsoi fets and soi finfets
- - Miaomiao Wang
  - Pranita Kulkarni
  - et al.
- 2010
- IRPS 2010
Challenges and opportunities of extremely thin SOI (ETSOI) CMOS technology for future low power and general purpose system-on-chip applications
- - A. Khakifirooz
  - Kangguo Cheng
  - et al.
- 2010
- VLSI-TSA 2010
A 0.063 μm² FinFET SRAM cell demonstration with conventional lithography using a novel integration scheme with aggressively scaled fin and gate pitch
- - Veeraraghvan S. Basker
  - Theodorus E. Standaert
  - et al.
- 2010
- VLSI Technology 2010
Ultra-thin-body and BOX (UTBB) Fully Depleted (FD) device integration for 22nm node and beyond
- - Q. Liu
  - A. Yagishita
  - et al.
- 2010
- VLSI Technology 2010
Stress liner proximity technique to enhance carrier mobility in high-κ metal gate MOSFETs
- - Dechao Guo
  - Kathryn Schonenberg
  - et al.
- 2009
- MRS Fall Meeting 2009
Extraction of effective oxide thickness for SOI FINFETs with high-κ/Metal gates using the body effect
- - Sujata Paul
  - Frank Yeh
  - et al.
- 2010
- IEEE Electron Device Letters
Fully depleted extremely thin SOI for mainstream 20nm low-power technology and beyond
- - Ali Khakifirooz
  - Kangguo Cheng
  - et al.
- 2010
- ISSCC 2010
Challenges and solutions of extremely thin SOI (ETSOI) for CMOS scaling to 22nm node and beyond
- - Kangguo Cheng
  - Ali Khakifirooz
  - et al.
- 2010
- CSTIC 2010
Challenges and solutions of FinFET integration in an SRAM cell and a logic circuit for 22 nm node and beyond
- - H. Kawasaki
  - V.S. Basker
  - et al.
- 2009
- IEDM 2009

Patents

- 08 Jul 2019
- US
- 10347759
Vertical Fet Structure
- 10 Jun 2019
- US
- 10319852
Forming Edram Unit Cell With Vfet And Via Capacitance
- 03 Jun 2019
- US
- 10312370
Forming A Sacrificial Liner For Dual Channel Devices
- 20 May 2019
- US
- 10297506
Hdp Fill With Reduced Void Formation And Spacer Damage
- 20 May 2019
- US
- 10297667
Fin Field-effect Transistor For Input/output Device Integrated With Nanosheet Field-effect Transistor
- 29 Apr 2019
- US
- 10276558
Vertical Fin Cmos Technology For Electrostatic Discharge Protection
- 01 Apr 2019
- US
- 10249754
Precise Junction Placement In Vertical Semiconductor Devices Using Etch Stop Layers
- 11 Mar 2019
- US
- 10229905
Electrostatic Discharge Devices And Methods Of Manufacture
- 11 Mar 2019
- US
- 10229983
Method And Structure Of Forming Fet With Ultra Low K Spacer
- 04 Mar 2019
- US
- 10224429
Precise Junction Placement In Vertical Semiconductor Devices Using Etch Stop Layers

Top collaborators

Huiming Bu

Title

Bio

Publications

Extremely thin SOI (ETSOI) technology: Past, present, and future

Hot-carrier degradation in undoped-body etsoi fets and soi finfets

Challenges and opportunities of extremely thin SOI (ETSOI) CMOS technology for future low power and general purpose system-on-chip applications

A 0.063 μm² FinFET SRAM cell demonstration with conventional lithography using a novel integration scheme with aggressively scaled fin and gate pitch

Ultra-thin-body and BOX (UTBB) Fully Depleted (FD) device integration for 22nm node and beyond

Stress liner proximity technique to enhance carrier mobility in high-κ metal gate MOSFETs

Extraction of effective oxide thickness for SOI FINFETs with high-κ/Metal gates using the body effect

Fully depleted extremely thin SOI for mainstream 20nm low-power technology and beyond

Challenges and solutions of extremely thin SOI (ETSOI) for CMOS scaling to 22nm node and beyond

Challenges and solutions of FinFET integration in an SRAM cell and a logic circuit for 22 nm node and beyond

Patents

Vertical Fet Structure

Forming Edram Unit Cell With Vfet And Via Capacitance

Forming A Sacrificial Liner For Dual Channel Devices

Hdp Fill With Reduced Void Formation And Spacer Damage

Fin Field-effect Transistor For Input/output Device Integrated With Nanosheet Field-effect Transistor

Vertical Fin Cmos Technology For Electrostatic Discharge Protection

Precise Junction Placement In Vertical Semiconductor Devices Using Etch Stop Layers

Electrostatic Discharge Devices And Methods Of Manufacture

Method And Structure Of Forming Fet With Ultra Low K Spacer

Precise Junction Placement In Vertical Semiconductor Devices Using Etch Stop Layers

Top collaborators

Dechao Guo

Dan J. Dechene

Hemanth Jagannathan

Nick Lanzillo