1024 Bit Bubble Memory Chip

A 1024-bit bubble memory chip having a storage density of 1.5 × 106 bits/in2 has been designed, fabricated, and tested. The chip organization consists of two identical, independent, 512-bit major-minor-loop configurations. All device functions have been operated at the chip level at 500 kHz. The bubble chip has been mounted in a ceramic module assembly containing a sense amplifier chip, the in-plane field coils, and the permanent-magnet bias field. All device functions have been operated at the module level at 100 kHz, and the nonvolatility capability has been established. © 1973, IEEE. All rights reserved.