Conference paper
A 40 GHz VCO with 9 to 15% tuning range in 0.13μm SOI CMOS
Neric Fong, Jean-Olivier Plouchart, et al.
VLSI Circuits 2002
A 23.5 GHz 32 nm SOI-CMOS PLL with 30% frequency tuning range features an adaptively biased VCO. The adaptive biasing scheme lowers the average PLL power consumption from 34 mW to 27.2 mW, while keeping the jitter below 1.3° RMS across all frequency bands. © 2004-2012 IEEE.
Neric Fong, Jean-Olivier Plouchart, et al.
VLSI Circuits 2002
Noah Zamdmer, Jonghae Kim, et al.
VLSI Technology 2004
Scott K. Reynolds, Arun S. Natarajan, et al.
RFIC 2010
Jean-Olivier Plouchart, Herschel Ainspan, et al.
EuMC 1999