Conference paper
A 2.6mW 370MHz-to-2.5GHz open-loop quadrature clock generator
Kyu-Hyoun Kim, Paul W. Coteus, et al.
ISSCC 2008
A single-chip 0.13μm CMOS optical transceiver incorporates sixteen 10Gb/s transmitter and receiver channels for a 160Gb/s aggregate bit rate. The transceiver is designed to support chip-to-chip board-level optical data buses and consumes 4.65mW/Gb/s with an area efficiency of 9.4Gb/s/mm2 per link. ©2008 IEEE.
Kyu-Hyoun Kim, Paul W. Coteus, et al.
ISSCC 2008
Chen Chen, Paul O. Leisher, et al.
IEEE Journal on Selected Topics in Quantum Electronics
Ilter Ozkaya, Alessandro Cevrero, et al.
IEEE JSSC
Clint L. Schow, Alexander V. Rylyakov, et al.
OFC 2011