Conference paper
Occupancy sampling for terabit CEE switches
Fredy D. Neeser, Nikolaos I. Chrysos, et al.
HOTI 2012
A four-terabit packet switch supporting long round-trip times is described. The switch uses a combined input- and crosspoint-queued structure with virtual output queuing at the ingress. The system is build from four different CMOS ASIC building blocks, using a total of 40 chips for the switching core and 64 fabric interface chips on the line cards. Benefits include high scalability, thoroughput and quality of service.
Fredy D. Neeser, Nikolaos I. Chrysos, et al.
HOTI 2012
Cyriel Minkenberg, François Abel, et al.
HPSR 2006
Cyriel Minkenberg
OFC 2015
Cyriel Minkenberg, German Rodriguez, et al.
PS 2015