Willard G. Bouricius, Edward P. Hsieh, et al.
IEEE TC
Paper
A Heuristic Algorithm for the Testing of Asynchronous Circuits
Abstract
This paper describes an algorithm for the computation of tests to detect failures in asynchronous sequential logic circuits. It is based upon an extension of the D-algorithm [1]. Discussion of experience with a program of the procedure is given. © 1971, IEEE. All rights reserved.
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