Conference paper
Tradeoffs in power-efficient issue queue design
Alper Buyuktosunoglu, David H. Albonesi, et al.
LPED 2002
This paper describes a study in which a PLA-based macro design of a small processer is carried out in the same technology as the original “random” logic design of the same processor. The objectives of the study were to determine gains or losses in “technology utilization” when a PLA-based approach is used to replace the more conventional “random” logic approach. The results in this case are a design of equal performance and density, with only one-third the power of the original design. Copyright © 1979 by The Institute of Electrical and Electronics Engineers, Inc.
Alper Buyuktosunoglu, David H. Albonesi, et al.
LPED 2002
Koushik K. Das, Rajiv V. Joshi, et al.
ESSCIRC 2003
Stanley E. Schuster
IEEE JSSC
Tak H. Ning, Peter W. Cook, et al.
IEEE JSSC