A synchronous interface for SoCs with multiple clock domains
Visvesh Sathe, Conrad Ziesler, et al.
SOCC 2004
Combinations of circuit techniques enabling tolerance to VT fluctuations in SRAM cell transistors during Read or Write operations and significant reductions in minimum operating voltage are reported. Implemented in a 9Kb × 74b PDSOI CMOS SRAM array with a conventional 65nm SRAM cell and an ABIST, these techniques, demonstrate VMIN of 0.58V and 0.40V/0.54V for single and dual VDD implementations respectively. The techniques consume a 10-12% overhead in area, improve performance marginally and also enable over 50% reduction in cell leakage with minimal circuit overhead.
Visvesh Sathe, Conrad Ziesler, et al.
SOCC 2004
Azeez Bhavnagarwala, Stephen Kosonocky, et al.
IEDM 2005
Jin Cai, Yuan Taur, et al.
VLSI Technology 2002
Rajiv Joshi, Rouwaida Kanj, et al.
IEEE Design and Test of Computers