Conference paper
Vanguard: A chip physical design system
Peter S. Hauge, Ellen J. Yoffa
DAC 1986
Because wiring a chip is so time consuming, it is highly desirable to be able to evaluate a particular placement of macros on a chip in terms of its wirability, or choose among several candidate placements, prior to any actual wiring. A method is presented to do this. The expected wire congestion is derived and the critical areas exposed, thereby enabling improvement of the chip layout. © 1985.
Peter S. Hauge, Ellen J. Yoffa
DAC 1986
Jerome M. Kurtzberg, Raymond D. Villani
IEEE TC
A.K. Mabatah, Ellen J. Yoffa, et al.
Physical Review B
Ellen J. Yoffa
Physical Review B