An integrated CAD methodology for evaluating MOSFET and parasitic extraction models and variability

An integrated computer-aided design (CAD) framework for evaluating MOSFET and layout parasitic extraction (LPE) models and circuit simulators used in the timing and power analysis of CMOS products is presented. This unified CAD methodology builds a step-wise understanding of the underlying parameter values in the models and their impact on circuit performance. A number of circuit experiments are included to extract the contributions of key MOSFET parameters and physical layout sensitive parasitic elements from circuit simulation results. This CAD setup thus allows easy and detailed comparison of different technologies, device models, and LPE tools to prevent possible bugs in the software as well as inaccuracies in device and parasitic models and timing tools. The software code to carry out the circuit simulations, analysis, and display of the results in an automated fashion has been specifically developed to support this framework. Some of the experiments designed for this work are also placed on the product chip for model-to-hardware correlation. The comparison of the hardware data to the model predictions points to the sources of any discrepancies and aids in tuning the product design to reflect changes in the technology as part of an overall design for manufacturing (DFM) platform © 2007 IEEE.