L.M. Terman, L.G. Heller
IEEE T-ED
The design and performance characteristics of a 128X64 MOS transistor memory is given. The storage cell used operates with a low standby power, 0.1 mW. The memory operates with a 12-ns access time, 35-ns read cycle time, and a 60-ns write cycle time. Copyright © 1966 by The Institute of Electrical and Electronics Engineers, Inc.
L.M. Terman, L.G. Heller
IEEE T-ED
A. Deutsch, W.D. Becker, et al.
IEEE Topical Meeting EPEPS 1996
L.G. Heller, L.M. Terman
IEEE JSSC
Christophe R. Tretz, C.T. Chuang, et al.
International Journal of Electronics