Keith A. Jenkins, Eduard Cartier, et al.
IEEE Electron Device Letters
Variability induced by bias temperature instability is an increasing concern in aggressively scaled CMOS technologies. To assess the stochastic nature of the instability, we demonstrate that the recently introduced voltage ramp stress methodology properly captures the variance component and thus can be used to study stochastic effects related to transistor design and gate-stack processes. © 2013 IEEE.
Keith A. Jenkins, Eduard Cartier, et al.
IEEE Electron Device Letters
Chia-Yu Chen, Qiushi Ran, et al.
IRPS 2011
Andreas Kerber, Eduard Cartier
IEEE Electron Device Letters
Kisik Choi, Takashi Ando, et al.
ECS Meeting 2013