Thomas E. Karis, C. Mark Seymour, et al.
Rheologica Acta
This paper reports all-silicon asymmetrically strained Tunnel FET architectures that feature improved subthreshold swing and Ion/I off characteristics. We demonstrate that a lateral strain profile corresponding to at least 0.2 eV band-gap shrinkage at the BTB source junction could act as an optimized performance Tunnel FET enabling the cancellation of the drain threshold voltage. To implement a real device, we demonstrate using GAA Si NW with asymmetric strain profile using two local stressor technologies to have >4-5 GPa peak of lateral uniaxial tensile stress in the Si NW. © 2010 Elsevier Ltd.
Thomas E. Karis, C. Mark Seymour, et al.
Rheologica Acta
Douglass S. Kalika, David W. Giles, et al.
Journal of Rheology
D.D. Awschalom, J.-M. Halbout
Journal of Magnetism and Magnetic Materials
B.A. Hutchins, T.N. Rhodin, et al.
Surface Science