The A to Z of SoCs
Reinaldo A. Bergamaschi, John Cohn
ICCAD 2002
Automating the design of system on a chip (SOC) using cores technique was presented. The cores or intellectual property (IP) blocks are used to quickly create SOC design with required complexity. The coreConnect architecture provides three buses namely processor local bus (PLB), on-chip peripheral bus (OPB) and device control-register (DCR) interconnects for interconnecting cores and custom logics. This technology brings a high-level abstraction to SOC design which enables easy reuse of existing components.
Reinaldo A. Bergamaschi, John Cohn
ICCAD 2002
Reinaldo A. Bergamaschi, Salil Raje
IEEE Design and Test of Computers
Reinaldo A. Bergamaschi
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Hiren D. Pate, Sandeep K. Shukla, et al.
DATE 2006