Control store implementation of a high performance VLSI CISC
J.H. Chang, H.H. Chao, et al.
MICRO Annual Workshop 1987
The logic and circuit design of an on-chip four-phase clock generator for the Micro-270 32-bit microprocessor, implemented as a finite-state machine, is described. The design combines the adjacent states of a state diagram, constructed using conventional techniques, to form a new state diagram. This reduces the number of states, logic and wiring complexity, and power and area consumption. The design also utilizes a pipelined and preconditioned organization to provide high-performance and spike-free clock pulses. It is very flexible, easily accommodating changes in the number of clock signals, clock loading and timing.
J.H. Chang, H.H. Chao, et al.
MICRO Annual Workshop 1987
F.Warren Shih, Tze-Chiang Lee, et al.
ICCD 1990
Pradip Bose
ICCD 1985
F.Warren Shih, H.H. Chao, et al.
IEEE ITC 1985