Steven C. Chan, Kenneth L. Shepard, et al.
IEEE Journal of Solid-State Circuits
Paper
Conquering noise in deep-submicron digital ICs
Abstract
As feature sizes decrease and clock frequencies increase, noise is becoming a greater concern in digital IC design. The authors describe a verification metric, noise stability, which guarantees functionality in the presence of noise, and a CAD technique, static noise analysis, for applying this metric on a chipwide basis.