L. Fredrickson, Razmik Karabed, et al.
IEEE Transactions on Magnetics
A VLSI trellis-coded partial-response (TCPR) codec module incorporating circuitry for three exploratory, improved trellis codes is presented. The architecture, implementation, and performance evaluation of a “partitioned'’ rate 8/10 matched-spectral-null (MSN) code are described in detail. The detector implementation uses a programmable, systolic architecture to realize a time-varying Add-Compare-Select (ACS) topology that rotates state-ACS assignments and periodically superimposes “auxiliary” survivor paths. The survivor memory unit requires only 3 bytes per interleave and is implemented using a two-stage, time-varying architecture combining register-exchange and traceback methods. The module was fabricated in 0.45 micron CMOS technology requiring less than 300 mW at 12 MB/sec. Selected experimental results for a variety of magnetic recording components are shown. © 1995 IEEE
L. Fredrickson, Razmik Karabed, et al.
IEEE Transactions on Magnetics
Razmik Karabed, P.H. Siegel
IEEE ICC 1989
C.B. Shung, P.H. Siegel, et al.
ICC 1990
P.H. Siegel
SPIE Optical Data Storage Topical Meeting 1984