Yang Yang, James Di Sarro, et al.
IRPS 2010
We present ESD device results from a 14nm FinFET SOI CMOS technology. Both fin-based and planar-based approaches are evaluated, with the planar-based diode design achieving 7 times higher failure current per silicon area. Planar-based diodes also show 25% higher failure current when Tsi increases by 40%.
Yang Yang, James Di Sarro, et al.
IRPS 2010
Souvick Mitra, Ephrem Gebreselasie, et al.
EOS/ESD 2015
Junjun Li, Robert Gauthier, et al.
EOS/ESD 2006
James Di Sarro, Kiran Chatty, et al.
IRPS 2007