Henry H.K. Tang, Conal E. Murray, et al.
IBM J. Res. Dev
This paper describes upsets of 65 nm flip-flops caused by Single-Event-Transients in clock-tree circuits. The upset rate is predicted through modeling, and compared to upset rates measured on a 65 nm test chip with 15 MeV carbon ions and 148 MeV protons. © 2009 IEEE.
Henry H.K. Tang, Conal E. Murray, et al.
IBM J. Res. Dev
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IEEE T-ED
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ANS Annual Conference 2008
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IBM J. Res. Dev