FPGA-based coprocessor for text string extraction
N.K. Ratha, A.K. Jain, et al.
Workshop CAMP 2000
This paper develops an analytical model for cache-reload transients and compares the model to observations based on several address traces. The cache-reload transient is the set of cache misses that occur when a process is reinitiated after being suspended temporarily. For example, an interrupt program that runs periodically experiences a reload transient at each initiation. The reload transient depends on the cache size and on the sizes of the footprints in the cache of the competing programs, where a program footprint is defined to be the set of lines in the cache in active use by the program. The model shows that the size of the transient is related to the normal distribution function. A simulation based on program-address traces shows excellent agreement between the model and the observations. © 1987, ACM. All rights reserved.
N.K. Ratha, A.K. Jain, et al.
Workshop CAMP 2000
Robert E. Donovan
INTERSPEECH - Eurospeech 2001
Gal Badishi, Idit Keidar, et al.
IEEE TDSC
Marshall W. Bern, Howard J. Karloff, et al.
Theoretical Computer Science