Nanbo Gong, W. Chien, et al.
VLSI Technology 2020
This talk discusses the development and optimization of a high-resolution semi-additive process for RDL. We discuss our approach to obtain optimal resist sidewalls and fine lines on a contact aligner. Then we show the final plating results with little to no undercut post seed layer etch by using a novel wet etch.
Nanbo Gong, W. Chien, et al.
VLSI Technology 2020
Heinz Schmid
FAME 2023
Pavlos Maniotis, Laurent Schares, et al.
SPIE OPTO 2021
Aaron Windsor, Jeremy Clark, et al.
JVSTB