Sonia Cafieri, Jon Lee, et al.
Journal of Global Optimization
Victor V256 is a partitionable message-passing multiprocessor with 256 processors, designed and in use at the IBM Thomas J. Watson Research Center. Our goals are to explore computer architectures based on the message-passing model and to use these architectures to solve real applications. We present the architecture of the Victor system, particularly its partitioning and nonintrusive monitoring. We discuss some of the programming environments on Victor, such as E-kernel, an embedding kernel developed for the support of program mapping and network reconfiguration. We review applications developed and run on Victor and discuss a few in depth, concluding with insights we have gained from this project.
Sonia Cafieri, Jon Lee, et al.
Journal of Global Optimization
Kafai Lai, Alan E. Rosenbluth, et al.
SPIE Advanced Lithography 2007
Khaled A.S. Abdel-Ghaffar
IEEE Trans. Inf. Theory
Thomas M. Cheng
IT Professional