Conference paper
Heterostructure bipolar transistors and circuits
S. Tiwari
ISCAS 1987
A 68020-based multiprocessor image processing system has been developed which is adaptable, flexible, extendable, modular, and fast. With the present four-processor system, it is possible to decode approximately 10 frames/s, where each frame contains 16384 pixels, using an image sequence compression algorithm developed by the authors. System components and operation are described along with present system performance; and areas for future improvements are considered.
S. Tiwari
ISCAS 1987
Vojin G. Oklobdzija
ISCAS 1987
Leonard Berman, Louise Trevillyan, et al.
ISCAS 1987
C.A. Gonzales, Lascoe A. Allman, et al.
Signal Processing: Image Communication