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A-SSCC 2006
A 10 GHz multiphase phase-locked loop (PLL) implemented in 90 nm bulk CMOS technology is presented that uses a bootstrapped NMOS inverter oscillator to obtain steeper clock edges, which may yield an improved jitter performance. The measured values for the rms and peak-to-peak jitter are better than 1 and 7 ps, respectively. © IEE 2005.
C. Kromer, G. Sialm, et al.
A-SSCC 2006
G.L. Bona, P. Buchmann, et al.
IEEE Photonics Technology Letters
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IEE/LEOS Summer Topical Meetings 1992
P.W. Epperlein, P. Buchmann, et al.
Applied Physics Letters