N. Blanc, P. Guéret, et al.
Applied Physics Letters
A 10 GHz multiphase phase-locked loop (PLL) implemented in 90 nm bulk CMOS technology is presented that uses a bootstrapped NMOS inverter oscillator to obtain steeper clock edges, which may yield an improved jitter performance. The measured values for the rms and peak-to-peak jitter are better than 1 and 7 ps, respectively. © IEE 2005.
N. Blanc, P. Guéret, et al.
Applied Physics Letters
K. Jackson, E.B. Flint, et al.
IEE/LEOS Summer Topical Meetings 1992
E. Marclay, D.J. Webb, et al.
Applied Physics Letters
P. Guéret, P. Buchmann, et al.
Applied Physics Letters