E. Marclay, D.J. Webb, et al.
Applied Surface Science
A 10 GHz multiphase phase-locked loop (PLL) implemented in 90 nm bulk CMOS technology is presented that uses a bootstrapped NMOS inverter oscillator to obtain steeper clock edges, which may yield an improved jitter performance. The measured values for the rms and peak-to-peak jitter are better than 1 and 7 ps, respectively. © IEE 2005.
E. Marclay, D.J. Webb, et al.
Applied Surface Science
F.R. Gfeller, P. Buchmann, et al.
ISLC 1992
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