A. Herkersdorf, P. Buchmann, et al.
International Zurich Seminar on Broadband Communications 2000
A 10 GHz multiphase phase-locked loop (PLL) implemented in 90 nm bulk CMOS technology is presented that uses a bootstrapped NMOS inverter oscillator to obtain steeper clock edges, which may yield an improved jitter performance. The measured values for the rms and peak-to-peak jitter are better than 1 and 7 ps, respectively. © IEE 2005.
A. Herkersdorf, P. Buchmann, et al.
International Zurich Seminar on Broadband Communications 2000
M. Kossel, C. Menolfi, et al.
Electronics Letters
E. Marclay, D.J. Webb, et al.
Applied Physics Letters
C. Harder, P. Buchmann, et al.
Electronics Letters