Conference paperA Comprehensive Study on the Pillar Size of OTS-PCM Memory with an Optimized Process and Scaling Trends Down to Sub-10 nm for SCM Applications
Conference paperSelf-aligned III-V MOSFETs: Towards a CMOS compatible and manufacturable technology solution
Conference paperDensity scaling with gate-all-around silicon nanowire MOSFETs for the 10 nm node and beyond
Conference paperHigh-performance Si1-xGex channel on insulator trigate PFETs featuring an implant-free process and aggressively-scaled fin and gate dimensions
