Conference paper
High Performance 0.1 μm CMOS Devices with 1.5 V Power Supply
Y. Taur, S.J. Wind, et al.
IEDM 1993
The process of transforming an architectural specification of a streamlined processor (the IBM 801) into a design specification suitable for input to a silicon compiler is described. Starting from that specification, the authors develop a description of combinational logic, latches and registers, hierarchically organized, which implement a pipelined version of the processing unit. This description is then automatically compiled down to the gate level in single ended cascode technology.
Y. Taur, S.J. Wind, et al.
IEDM 1993
R. Brayton, R. Willoughby
IEEE Transactions on Electronic Computers
Giovanni De Micheli
ICCAD 1985
Chih-Liang Chen
VLSI Circuits 1991