R. Puri, C.T. Chuang
IEEE International SOI Conference 1998
The author presents a high-speed low-power NTL (non-threshold-logic)-based push-pull circuit featuring a complementary emitter-follower driver. Compared with the standard NTL circuit, this circuit offers a much better balance between the pull-up and pull-down delay, improved scalability, and superior load driving capability. Simulation results based on a 0.8-μm double-poly self-aligned complementary bipolar technology indicate that, at a power consumption of 1.22 mW/gate, the circuit achieves a load driving capability of 70 ps/pF, about a four-times improvement over the 310-ps/pF for the standard NTL circuit.
R. Puri, C.T. Chuang
IEEE International SOI Conference 1998
W. Hwang, C.T. Chuang, et al.
VLSI-TSA 2001
Satish Kumar, Rajiv V. Joshi, et al.
ICICDT 2007
P.F. Lu, C.T. Chuang
CICC 1992