Conference paper
SEAS: A System for Early Analysis of SoCs
Reinaldo A. Bergamaschi, Youngsoo Shin, et al.
CODES+ISSS 2003
Verifying equivalence of the behavioral specification and scheduled implementation is a significant problem in high-level synthesis, because scheduling changes the cycle-by-cycle behavior. The authors present a practical method for comparing simulation results for the two using the same vectors.
Reinaldo A. Bergamaschi, Youngsoo Shin, et al.
CODES+ISSS 2003
Reinaldo A. Bergamaschi, Andreas Kuehlmann
IEEE Transactions on VLSI Systems
Nagu Dhanwada, Reinaldo A. Bergamaschi, et al.
Des Autom Embedded Syst
Martin Ohmacht, Reinaldo A. Bergamaschi, et al.
IBM J. Res. Dev