Martin Ohmacht, Reinaldo A. Bergamaschi, et al.
IBM J. Res. Dev
Verifying equivalence of the behavioral specification and scheduled implementation is a significant problem in high-level synthesis, because scheduling changes the cycle-by-cycle behavior. The authors present a practical method for comparing simulation results for the two using the same vectors.
Martin Ohmacht, Reinaldo A. Bergamaschi, et al.
IBM J. Res. Dev
Reinaldo A. Bergamaschi
IEEE Design and Test of Computers
Shaojie Wang, Sharad Malik, et al.
DATE 2003
Nagu Dhanwada, Reinaldo A. Bergamaschi, et al.
Des Autom Embedded Syst