Conference paper
Redesign using state splitting
Raul Camposano, Reinaldo A. Bergamaschi
EDAC 1990
Verifying equivalence of the behavioral specification and scheduled implementation is a significant problem in high-level synthesis, because scheduling changes the cycle-by-cycle behavior. The authors present a practical method for comparing simulation results for the two using the same vectors.
Raul Camposano, Reinaldo A. Bergamaschi
EDAC 1990
Reinaldo A. Bergamaschi, Yunjian W. Jiang
DAC 2003
Reinaldo A. Bergamaschi, Salil Raje, et al.
IEEE Transactions on VLSI Systems
Reinaldo A. Bergamaschi, Andreas Kuehlmann
IEEE Transactions on VLSI Systems