Conference paper
Early and accurate analysis of SoCs: Oxymoron or real?
Reinaldo A. Bergamaschi
SLIP 2004
Verifying equivalence of the behavioral specification and scheduled implementation is a significant problem in high-level synthesis, because scheduling changes the cycle-by-cycle behavior. The authors present a practical method for comparing simulation results for the two using the same vectors.
Reinaldo A. Bergamaschi
SLIP 2004
Daniel Brand, Reinaldo A. Bergamaschi, et al.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Reinaldo A. Bergamaschi, Youngsoo Shin, et al.
CODES+ISSS 2003
Raul Camposano, Reinaldo A. Bergamaschi
EDAC 1990