Conference paper
Performance test case generation for microprocessors
Pradip Bose
VTS 1998
We present some results on families of balanced binary error-correcting codes that extend those in the literature. The idea is to consider balanced blocks as symbols over an alphabet and to construct error-correcting codes over that alphabet. Encoding and decoding procedures are presented. Several improvements to the general construction are also discussed. © 1989 IEEE
Pradip Bose
VTS 1998
John M. Boyer, Charles F. Wiecha
DocEng 2009
Michael C. McCord, Violetta Cavalli-Sforza
ACL 2007
Frank R. Libsch, S.C. Lien
IBM J. Res. Dev