David Bernstein, Haran Boral, et al.
IEEE TC
Chaining is the ability to pipeline two or more vector instructions on Cray-1 like machines. We show how to optimally use this feature to compute (vector) expression trees, in the context of automatic code-generation. We present a linear-time scheduling algorithm for finding an optimal order of evaluation for a machine with a bounded number of registers. © 1986, ACM. All rights reserved.
David Bernstein, Haran Boral, et al.
IEEE TC
Amnon Joseph, Ron Y. Pinter
Integration, the VLSI Journal
Reuven Bar-Yehuda, Jack A. Feldman, et al.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Shmuel Wimer, Ron Y. Pinter, et al.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems