Statistical fault injection
Pradeep Ramachandran, Prabhakar Kudva, et al.
DSN 2008
Most high-level synthesis tools for asynchronous circuits take descriptions in concurrent hardware description languages and generate networks of macromodules or handshake components. In this paper, we propose a peephole optimizer for these networks. Our peephole optimizer first deduces an equivalent blackbox behavior for the network using Dill's trace-theoretic parallel composition operator. It then applies a new procedure called burst-mode reduction to obtain burst-mode machines from the deduced behavior. In a significant number of examples, our optimizer achieves gate-count improvements by a factor of five, and speed (cycle-time) improvements by a factor of two. Burst-mode reduction can be applied to any macromodule network that is delay insensitive as well as deterministic. A significant number of asynchronous circuits, especially those generated by asynchronous high-level synthesis tools, fall into this class, thus making our procedure widely applicable. © 1999 IEEE.
Pradeep Ramachandran, Prabhakar Kudva, et al.
DSN 2008
Rupesh Raj Karn, Prabhakar Kudva, et al.
IEEE Access
Carl Bender, Pia N. Sanda, et al.
IBM J. Res. Dev
Jude A. Rivers, Pradip Bose, et al.
IBM J. Res. Dev