Editorial

01 Jun 2021

RFIC 2020 Guest Editorial

Conference paper

A Scalable Heterogeneous AiP Module for a 256-Element 5G Phased Array

Duixian Liu, Xiaoxiong Gu, et al.

ECTC 2023

Conference paper

An integral path self-calibration scheme for a 20.1-26.7GHz dual-loop PLL in 32nm SOI CMOS

Mark Ferriss, Jean-Olivier Plouchart, et al.

VLSI Circuits 2012

Conference paper

A 13.1-to-28GHz fractional-N PLL in 32nm SOI CMOS with a ΔΣ noise-cancellation scheme

Mark Ferriss, Bodhisatwa Sadhu, et al.

ISSCC 2015

Conference paper

A 60GHz packaged switched beam 32nm CMOS TRX with broad spatial coverage, 17.1dBm peak EIRP, 6.1dB NF at < 250mW

Bodhisatwa Sadhu, Alberto Valdes-Garcia, et al.

RFIC 2016

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