Profile-driven generation of trace samples
P.K. Dubey, Ravi Nair
ICCD 1996
Recent limit studies on instruction-level parallel processing, based on non-numeric applications, have reported significant performance gains from speculative execution of multiple control flows. This paper describes a new single-program speculative multithreading (SPSM) architecture, which can be viewed as an extension of any existing single-thread architecture. It enables speculative fetch, decode, and execution from multiple program locations simultaneously. Instruction threads are generated at compile-time using control dependence analysis. Inter-thread data dependences are also analyzed at compile-time. However, resource binding of instructions is performed only at run time, to offer binary compatibility across different implementations. New thread generation algorithms, being prototyped in a version of the TOBEY compiler, are also described. The SPSM architecture includes novel fork/suspend instructions which are used to identify independent instruction threads, and also to specify compile-time control flow speculations associated with inter-thread dependences.
P.K. Dubey, Ravi Nair
ICCD 1996
P.K. Dubey, Arvind Krishna, et al.
MASCOTS 1995
Rudolph N. Rechtschaffen, K. Ekanadham
PACT 1994
David Bernstein, D. Cohen, et al.
PACT 1994