Special series on harsh chips

Augusto Vega; Alper Buyuktosunoglu; Pradip Bose

doi:10.1109/MM.2014.102

IEEE Micro

Review

01 Nov 2014

Special series on harsh chips

Download paper

Abstract

This introduction to the special series discusses the emerging field of harsh-environment-capable chips, or harsh chips. It also introduces the first two Harsh Chips articles in the issue.

Conference paper

SMT-centric power-aware thread placement in chip multiprocessors

Augusto Vega, Alper Buyuktosunoglu, et al.

PACT 2013

Conference paper

Software-controlled priority characterization of POWERS processor

Carlos Boneti, Francisco J. Cazorla, et al.

ISCA 2008

Conference paper

Very low voltage (VLV) design

Ramon Bertran, Pradip Bose, et al.

ICCD 2017

Conference paper

Validation of Turandot, a fast processor model for microarchitecture exploration

Mayan Moudgill, Pradip Bose, et al.

IEEE International Performance, Computing and Communications Conference, Proceedings 1999

View all publications

Abstract

Related

SMT-centric power-aware thread placement in chip multiprocessors

Software-controlled priority characterization of POWERS processor

Very low voltage (VLV) design

Validation of Turandot, a fast processor model for microarchitecture exploration