P. Alnot, D.J. Auerbach, et al.
Surface Science
This article describes various techniques for applying strain to current and future complementary metal-oxide-semiconductor (CMOS) channels to boost CMOS performance. A brief history of both biaxial and uniaxial strain engineering in planar CMOS technology is discussed. Scalability challenges associated with process-induced uniaxial strain in sub-22 nm CMOS is highlighted in view of shrinking device dimensions and 3D device architecture (such as fin field-effect transistors [FinFETs]). Non-uniform strain relaxation in patterned geometries in tight pitch two- and three-dimensional devices is addressed. A case is made that the future scalable strain platform will require a combination of biaxial strain at wafer level in conjunction with local uniaxial strain. Finally, potential application of strain engineering to advanced III-V metal oxide semiconductor FET channels will be examined. © 2014 Materials Research Society.
P. Alnot, D.J. Auerbach, et al.
Surface Science
B.A. Hutchins, T.N. Rhodin, et al.
Surface Science
Heinz Schmid, Hans Biebuyck, et al.
Journal of Vacuum Science and Technology B: Microelectronics and Nanometer Structures
Arvind Kumar, Jeffrey J. Welser, et al.
MRS Spring 2000