Conference paper
The dawn of 22nm era: Design and CAD challenges
Ruchir Puri, David S. Kung
VLSID/Embedded 2010
In this paper, we discuss timing closure for high performance microprocessor designs. Aggressive cycle time and deep submicron technology scaling introduce a myriad of problems that are not present in the ASIC domain. The impact of these problems on floorplanning, placement, clocking and logic synthesis is described. We present ideas and potential solutions for tackling these problems.
Ruchir Puri, David S. Kung
VLSID/Embedded 2010
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David S. Kung
DAC 1998
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DAC 2004