Conference paper
0.5 μm CMOS device design and characterization
H.I. Hanafi, M.R. Wordeman, et al.
ESSDERC 1987
The turn-on delay time of the vertical parasitic bipolar device of a CMOS transistor after the application of a latch-up triggering signal to forward bias the n+ source junction was studied. We found that the delay time for the device on an epitaxial CMOS transistor is in the order of a few nanoseconds, which is much shorter than that on a nonepitaxial CMOS transistor. Copyright © 1987 by The Institute of Electrical and Electronics, Inc.
H.I. Hanafi, M.R. Wordeman, et al.
ESSDERC 1987
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IEDM 1990
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