Phillip J. Restle, Albert E. Ruehli, et al.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
This paper presents a new approach to global clock distribution in which tree-driven grids are augmented with on-chip spiral inductors to resonate the clock capacitance. In this scheme, the energy of the fundamental frequency resonates between electric and magnetic forms, with the reduced admittance of the clock network allowing for significantly lower gain requirements in the buffering network. The substantial improvements in jitter and power resulting from this approach are presented using measurement results from two test chips, one fabricated in a 90-nm and the other in a 0.18-μm CMOS technology.
Phillip J. Restle, Albert E. Ruehli, et al.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Noah Sturcken, Eugene J. O'Sullivan, et al.
IEEE JSSC
Liang-Teck Pang, Phillip J. Restle, et al.
VLSI Circuits 2012
Brian Vanderpool, Phillip J. Restle, et al.
IEEE JSSC