A shorted global clock design for multi-GHz 3D stacked chips
Liang-Teck Pang, Phillip J. Restle, et al.
VLSI Circuits 2012
This paper presents a new approach to global clock distribution in which tree-driven grids are augmented with on-chip spiral inductors to resonate the clock capacitance. In this scheme, the energy of the fundamental frequency resonates between electric and magnetic forms, with the reduced admittance of the clock network allowing for significantly lower gain requirements in the buffering network. The substantial improvements in jitter and power resulting from this approach are presented using measurement results from two test chips, one fabricated in a 90-nm and the other in a 0.18-μm CMOS technology.
Liang-Teck Pang, Phillip J. Restle, et al.
VLSI Circuits 2012
Steven C. Chan, Kenneth L. Shepard, et al.
ICCD 2003
Rex Berridge, Robert M. Averill III, et al.
IBM J. Res. Dev
Steven C. Chan, Kenneth L. Shepard, et al.
IEEE Journal of Solid-State Circuits