Conference paper
Technology adaptation in logic synthesis
William H. Joyner, Louise H. Trevillyan, et al.
DAC 1986
A protocol verifier using symbolic execution has been designed and implemented as part of a general verifier (oriented towards microcode). This part describes how this method works for communication protocols involving timing assumptions, state changes depending on message contents, unreliable medium, an arbitrary number of communicating processes, etc. The method can detect design errors such as deadlock and tempo-blocking; in addition the user can add his own assertions to express other desired properties. © 1978.
William H. Joyner, Louise H. Trevillyan, et al.
DAC 1986
Daniel Brand, Vuay S. Iyengar
IEEE TC
Daniel Brand, Pitro Zafiropulo
Journal of the ACM
Daniel Brand
ACM SIGPLAN Notices