Multi-bit upsets in 65nm SOI SRAMs
Ethan H. Cannon, Michael S. Gordon, et al.
IRPS 2008
This paper investigates the n-type vertical slit FET (VeSFET) performance at 7-nm node and beyond by TCAD simulation. VeSFET is a twin-gate device with 3-D monolithic integration-friendly vertical terminals and horizontal channel manufactured based on SOI wafer with conventional CMOS fabrication hardware. The second gate provides the capability of transistor behavior adjustment and the potential for advanced circuit designs. The results show that VeSFET can provide high ΔVt/Vg2s, and competitive drive capability with respect to a reference FinFET of comparable dimensions..
Ethan H. Cannon, Michael S. Gordon, et al.
IRPS 2008
Tenko Yamashita, Veeraraghvan S. Basker, et al.
VLSI Technology 2011
A.J. KleinOsowski, Ethan H. Cannon, et al.
IBM J. Res. Dev
Aj Kleinosowski, Ethan H. Cannon, et al.
IEEE TNS