Andreas Kerber, Eduard Cartier
IEEE Electron Device Letters
A novel voltage-ramp-stress (VRS) methodology is introduced for bias temperature instability testing of metal-gate/high-k (MG/HK) CMOS devices. Results from VRS are compared with the constant-voltage-stress procedure. It is demonstrated that the voltage and time dependence measured with both methods agree well with each other. These findings make the VRS test the preferred procedure for screening and process monitoring of MG/HK CMOS technologies because the test always yields measurable shifts and little knowledge about gate-stack details is required. © 2009 IEEE.
Andreas Kerber, Eduard Cartier
IEEE Electron Device Letters
Barry P. Linder, Eduard Cartier, et al.
IRPS 2009
Andreas Kerber, Eduard Albert Cartier
IEEE T-DMR
Takashi Ando, B. Kannan, et al.
VLSI Technology 2014