Qing Li, Zhigang Deng, et al.
IEEE T-MI
We consider the problem of implementing a wait-free regular register from storage components prone to Byzantine faults. We present a simple, efficient, and self-contained construction of such a register. Our construction utilizes a novel building block, called a 1-regular register, which can be efficiently implemented from Byzantine fault-prone components. © 2006 Elsevier B.V. All rights reserved.
Qing Li, Zhigang Deng, et al.
IEEE T-MI
Beomseok Nam, Henrique Andrade, et al.
ACM/IEEE SC 2006
Heinz Koeppl, Marc Hafner, et al.
BMC Bioinformatics
Fan Jing Meng, Ying Huang, et al.
ICEBE 2007