Maciel Zortea, Miguel Paredes, et al.
IGARSS 2021
This paper describes a recent system-level trend toward the use of massive on-chip parallelism combined with efficient hardware accelerators and integrated networking to enable new classes of applications and computing-systems functionality. This system transition is driven by semiconductor physics and emerging network-application requirements. In contrast to general-purpose approaches, workload and network-optimized computing provides significant cost, performance, and power advantages relative to historical frequency-scaling approaches in a serial computational model. We highlight the advantages of on-chip network optimization that enables efficient computation and new services at the network edge of the data center. Software and application development challenges are presented, and a service-oriented architecture application example is shown that characterizes the power and performance advantages for these systems. We also discuss a roadmap for next-generation systems that proportionally scale with future networking bandwidth growth rates and employ 3-D chip integration methods for design flexibility and modularity. ©Copyright 2010 by International Business Machines Corporation.
Maciel Zortea, Miguel Paredes, et al.
IGARSS 2021
William Hinsberg, Joy Cheng, et al.
SPIE Advanced Lithography 2010
Nanda Kambhatla
ACL 2004
Eric Price, David P. Woodruff
FOCS 2011