An Eight-Lane 7-Gb/s/pin Source Synchronous Single-Ended RX with Equalization and Far-End Crosstalk Cancellation for Backplane Channels
- Cosimo Aprile
- Alessandro Cevrero
- et al.
- 2018
- IEEE JSSC
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44 results for Yusuf Leblebici
A 64-Gb/s 1.4-pJ/b NRZ Optical Receiver Data-Path in 14-nm CMOS FinFET
- Ilter Ozkaya
- Alessandro Cevrero
- et al.
- 2017
- IEEE JSSC
Implementation of Low-Power 6-8 b 30-90 GS/s Time-Interleaved ADCs With Optimized Input Bandwidth in 32 nm CMOS
- Lukas Kull
- J. Pliva
- et al.
- 2016
- IEEE JSSC
A 3.1 mW 8b 1.2 GS/s single-Channel asynchronous SAR ADC with alternate comparators for enhanced speed in 32 nm digital SOI CMOS
- Lukas Kull
- Thomas Toifl
- et al.
- 2013
- IEEE JSSC
A 4.8pJ/b 56Gb/s ADC-Based PAM-4 Wireline Receiver Data-Path with Cyclic Prefix in 14nm FinFET
- Gain Kim
- Lukas Kull
- et al.
- 2019
- A-SSCC 2019
Non-filamentary non-volatile memory elements as synapses in neuromorphic systems
- Alessandro Fumarola
- Yusuf Leblebici
- et al.
- 2019
- NVMTS 2019
Multi-ReRAM synapses for artificial neural network training
- Irem Boybat
- Cecilia Giovinazzo
- et al.
- 2019
- ISCAS 2019
Impact of conductance drift on multi-PCM synaptic architectures
- Irem Boybat
- S. R. Nandakumar
- et al.
- 2018
- NVMTS 2018
Online Feature Learning from a non-i.i.d. Stream in a Neuromorphic System with Synaptic Competition
- Stanislaw Wozniak
- Angeliki Pantazi
- et al.
- 2018
- IJCNN 2018
Parallel Implementation Technique of Digital Equalizer for Ultra-High-Speed Wireline Receiver
- Gain Kim
- Lukas Kull
- et al.
- 2018
- ISCAS 2018