Integration of intra chip stack fluidic cooling using thin-layer solder bonding
- Yassir Madhour
- Michael Zervas
- et al.
- 2013
- 3DIC 2013
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44 results for Yusuf Leblebici
A 35mW8 b 8.8 GS/s SAR ADC with low-power capacitive reference buffers in 32nm Digital SOI CMOS
- Lukas Kull
- Thomas Toifl
- et al.
- 2013
- VLSI Circuits 2013
Pin-shape assessment for interlayer-cooled chip stacks with periodic boundary condition modeling
- Gözde Töral
- Roland Bender
- et al.
- 2010
- THERMINIC 2010
Heat-removal performance scaling of interlayer cooled chip stacks
- Thomas Brunschwiler
- Stephan Paredes
- et al.
- 2010
- ITherm 2010
Validation of the porous-medium approach to model interlayer-cooled 3D-chip stacks
- T. Brunschwiler
- S. Paredes
- et al.
- 2009
- 3DIC 2009
A 1.8V 12-bit 230-MS/s pipeline ADC in 0.18μm CMOS technology
- Thomas Liechti
- Armin Tajalli
- et al.
- 2008
- APCCAS 2008
Case study of fault-tolerant architectures for 90nm CMOS crythographic cores
- Milos Stanisavljevic
- Frank Kagan Gürkaynak
- et al.
- 2007
- PRIME 2007
Design and realization of a fault-tolerant 90nm CMOS cryptographic engine capable of performing under massive defect density
- Milos Stanisavljevic
- Frank Kagan Gürkaynak
- et al.
- 2007
- GLSVLSI 2007
A 90nm CMOS Cryptographic Core with Improved Fault-Tolerance in Presence of Massive Defect Density
- Milos Stanisavljevic
- Frank Kagan Gürkaynak
- et al.
- 2007
- Nano-Net 2007
Bidirectional Non-Filamentary RRAM as an Analog Neuromorphic Synapse, Part II: Impact of Al/Mo/Pr0.7Ca0.3MnO3 Device Characteristics on Neural Network Training Accuracy
- Alessandro Fumarola
- S. Sidler
- et al.
- 2018
- IEEE J-EDS