'Timing Closure by Design,' a high frequency microprocessor design methodology
- S.D. Posluszny
- Naoaki Aoki
- et al.
- 2000
- DAC 2000
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10 results for Naoaki Aoki
1GHz fully pipelined 3.7ns Address access time 8kx1024 embedded DRAM macro
- O. Takahashi
- S. Dhong
- et al.
- 2000
- ISSCC 2000
A 1GHz single-issue 64b powerPC processor
- H.P. Hofstee
- Naoaki Aoki
- et al.
- 2000
- ISSCC 2000
1.6 ns access, 1 GHz two-way set-predicted and sum-indexed 64-kByte data cache
- Joel Silberman
- Naoaki Aoki
- et al.
- 2000
- VLSI Circuits 2000
Design methodology for a 1.0 GHz microprocessor
- S.D. Posluszny
- Naoaki Aoki
- et al.
- 1998
- ICCD 1998
690ps read-access latency register file for a GHz integer microprocessor
- O. Takahashi
- Joel Silberman
- et al.
- 1998
- ICCD 1998
1 GHz logic circuits with sense amplifiers
- O. Takahashi
- Naoaki Aoki
- et al.
- 1998
- VLSI Circuits 1998
1-GHz fully pipelined 3.7-ns address access time 8 k × 1024 embedded synchronous DRAM macro
- Osamu Takahashi
- Sang H. Dhong
- et al.
- 2000
- IEEE Journal of Solid-State Circuits
A 1-GHz logic circuit family with sense amplifiers
- O. Takahashi
- Naoaki Aoki
- et al.
- 1999
- IEEE Journal of Solid-State Circuits
1.0-GHz single-issue 64-bit PowerPC integer processor
- Joel Silberman
- Naoaki Aoki
- et al.
- 1998
- IEEE Journal of Solid-State Circuits