SOI 90-nm ring oscillator sub-ps model-hardware correlation and parasitic-aware optimization leading to 1.94-ps switching delay
- Jean-Olivier Plouchart
- Jonghae Kim
- et al.
- 2005
- IEDM 2005
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6 results for W. Clark
Dual stress liner for high performance sub-45nm gate length SOI CMOS manufacturing
- H.S. Yang
- R. Malik
- et al.
- 2004
- IEDM 2004
A 45nm low power bulk technology featuring carbon co-implantation and laser anneal on 45°-rotated substrate
- J. Yuan
- V. Chan
- et al.
- 2008
- ICSICT 2008
Low-frequency noise of 90nm nFETs: Hot-carrier degradation and deuterium effect
- M. Erturk
- R. Anna
- et al.
- 2004
- SiRF 2004
Body voltage and history effect sensitivity to key device parameters in 90nm PD-SOI
- S. Kawanaka
- M.B. Ketchen
- et al.
- 2004
- IEEE International SOI Conference 2004
The combined effects of deuterium anneals and deuterated barrier-nitride processing on hot-electron degradation in MOSFET's
- Thomas G. Ference
- Jay S. Burnham
- et al.
- 1999
- IEEE Transactions on Electron Devices