A 45 nm CMOS node Cu/low-k/ ULtra low-k PECVD SiCOH (k=2.4) BEOL technology
- S. Sankaran
- S. Arai
- et al.
- 2006
- IEDM 2006
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10 results for S. Greco
High performance 45-nm SOI technology with enhanced strain, porous low-k BEOL, and immersion lithography
- S. Narasimha
- K. Onishi
- et al.
- 2006
- IEDM 2006
A high performance 90 nm SOI technology with 0.992 μm2 6T-SRAM cell
- Mukesh Khare
- S. Ku
- et al.
- 2002
- IEDM 2002
A High-Density 6.9 sq. pm Embedded SRAM Cell in a High-Performance 0.25 μm-Generation CMOS Logic Technology
- S. Subbanna
- P. Agnello
- et al.
- 1996
- IEDM 1996
Predicting and reducing substrate induced focus error
- Bernhard Liegl
- Brian Sapp
- et al.
- 2010
- SPIE Advanced Lithography 2010
Integration of copper and fluorosilicate glass for 0.18 μm interconnections
- E. Barth
- T. Ivers
- et al.
- 2000
- IITC 2000
0.18 μm high-performance logic technology
- S.W. Crowder
- S. Greco
- et al.
- 1999
- VLSI Technology 1999
Electromigration challenges for nanoscale Cu wiring
- C.-K. Hu
- L. Gignac
- et al.
- 2008
- International Workshop on Stress-Induced Phenomena in Metallization 2008
Predicting substrate-induced focus error
- Bernhard Liegl
- Brian Sapp
- et al.
- 2010
- Journal of Micro/Nanolithography, MEMS, and MOEMS
Opportunities and challenges in ultra low k dielectrics for interconnect applications
- S. Purushothaman
- S.V. Nitta
- et al.
- 2001
- Technical Digest-International Electron Devices Meeting