Sub-60 nm physical gate length SOI CMOS
- I.Y. Yang
- K. Chen
- et al.
- 1999
- IEDM 1999
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4 results for W. Chu
High performance 0.18 μm SOI CMOS technology
- E. Leobandung
- E. Barth
- et al.
- 1999
- IEDM 1999
Characterization of Across-device Linewidth Variation (ADLV) for 65 nm logic SRAM using CDSEM and linewidth roughness algorithms
- W. Chu
- C. Radens
- et al.
- 2006
- SPIE Advanced Lithography 2006
Process window metrology
- Christopher P. Ausschnitt
- W. Chu
- et al.
- 2000
- SPIE Advanced Lithography 2000