A critical analysis of sampling-based reconstruction methodology for dielectric breakdown systems (BEOL/MOL/FEOL)
- Ernest Y. Wu
- James Stathis
- et al.
- 2015
- IRPS 2015
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96 results for Barry P. Linder
Analyzing path delays for accelerated testing of logic chips
- Emily Ray
- Barry P. Linder
- et al.
- 2015
- IRPS 2015
Self-heating characterization of FinFET SOI devices using 2D time resolved emission measurements
- Franco Stellari
- Keith A. Jenkins
- et al.
- 2015
- IRPS 2015
High performance 14nm SOI FinFET CMOS technology with 0.0174μm2 embedded DRAM and 15 levels of Cu metallization
- C.-H.C-H. Lin
- Brian Greene
- et al.
- 2014
- IEDM 2014
Reliability challenges for the 10nm node and beyond
- 2014
- IEDM 2014
Simple Gate Metal Anneal (SIGMA) stack for FinFET Replacement Metal Gate toward 14nm and beyond
- Takashi Ando
- B. Kannan
- et al.
- 2014
- VLSI Technology 2014
Spatial mapping of non-uniform time-to-breakdown and physical evidence of defect clustering
- Ernest Y. Wu
- Baozhen Li
- et al.
- 2014
- VLSI Technology 2014
Combined ramp voltage stress and constant voltage stress for optimal BTI voltage acceleration and lifetime modeling
- Barry P. Linder
- Takashi Ando
- 2014
- IRPS 2014
Deposited ALD SiO2 high-k/metal gate interface for high voltage analog and I/O devices on next generation alternative channels and FINFET device structures
- S. Siddiqui
- M.M. Chowdhury
- et al.
- 2013
- ECS Meeting 2013
Metal Gate/High-κ dielectric gate stack reliability; or how i learned to live with trappy oxides
- Barry P. Linder
- Eduard Cartier
- et al.
- 2013
- ECS Meeting 2013